Triple
T6961671
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Intel Core Solo |
E161382
|
entity |
| Predicate | instructionSetWidth |
P4121
|
FINISHED |
| Object | 32-bit |
—
|
LITERAL FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: 32-bit | Statement: [Intel Core Solo, instructionSetWidth, 32-bit]
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: instructionSetWidth Context triple: [Intel Core Solo, instructionSetWidth, 32-bit]
-
A.
instructionSetSize
Indicates the size or number of instructions defined in an instruction set.
-
B.
instructionLength
Indicates the duration or amount of time required to carry out a given instruction or operation.
-
C.
instructionSetType
Indicates the type or category of an instruction set associated with a processor or computing architecture.
-
D.
bitWidth
chosen
Indicates the number of bits used to represent or encode a given value, type, or data element.
-
E.
numberOfGeneralPurposeRegisters
Indicates the quantity of general-purpose registers associated with or available in a given computing context.
- F. None of above.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69c68853cff881908439d488924a8283 |
completed | March 27, 2026, 1:38 p.m. |
| NER | Named-entity recognition | batch_69c6daf07e3481909aa79b8e0f1b1be7 |
completed | March 27, 2026, 7:30 p.m. |
| PD | Predicate disambiguation | batch_69c6d7c0b0a08190b262dfc94992994d |
completed | March 27, 2026, 7:17 p.m. |
Created at: March 27, 2026, 2:30 p.m.