Triple
T6327994
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Analytical Engine |
E141905
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | historical computer architecture |
C20330
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: historical computer architecture Context triple: [Analytical Engine, instanceOf, historical computer architecture]
-
A.
computer architecture
Computer architecture is the conceptual design and organization of a computer system’s fundamental components and their interactions, defining how hardware and software work together to execute instructions efficiently.
-
B.
microprocessor architecture
Microprocessor architecture is the conceptual design and organization of a computer’s central processing unit, defining its instruction set, data paths, control logic, memory hierarchy, and interfaces to efficiently execute programs.
-
C.
stored-program computer
A stored-program computer is a computing system in which both program instructions and data are stored in the same read-write memory, allowing the machine to modify and execute instructions sequentially or conditionally.
-
D.
RISC architecture
A RISC architecture is a computer processor design that uses a small, highly optimized set of simple instructions to achieve high performance through efficient pipelining and parallelism.
-
E.
electronic stored-program computer
An electronic stored-program computer is a digital machine that executes instructions and processes data by electronically manipulating binary information according to programs held in its memory.
- F. None of above. chosen
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69c008d201748190917e69c41ba3f978 |
completed | March 22, 2026, 3:20 p.m. |
Created at: March 22, 2026, 4:29 p.m.