Triple

Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).

Phrase: branching-time temporal logic CTL* | Statement: [E. Allen Emerson, notableWork, branching-time temporal logic CTL*]

Target entity: branching-time temporal logic CTL*
Context triple: [E. Allen Emerson, notableWork, branching-time temporal logic CTL*]

• A. Temporal Logic of Actions
  Temporal Logic of Actions is a formal framework for specifying and reasoning about concurrent and distributed systems using temporal logic to describe system behaviors over time.
• B. Temporal Verification of Reactive Systems
  "Temporal Verification of Reactive Systems" is a foundational book in formal methods that presents rigorous techniques for specifying and verifying the correctness of reactive and concurrent systems using temporal logic.
• C. Model Checking (book)
  "Model Checking" is a foundational textbook that systematically presents the theory and practice of using automated verification techniques to prove correctness properties of hardware and software systems.
• D. Symbolic Model Checking
  Symbolic Model Checking is a formal verification technique that uses symbolic representations, such as binary decision diagrams, to efficiently verify properties of hardware and software systems with very large state spaces.
• E. Satisfiability Modulo Theories (SMT)
  Satisfiability Modulo Theories (SMT) is a framework in computer science and mathematical logic for deciding the satisfiability of logical formulas with respect to background theories such as arithmetic, bit-vectors, arrays, and data types, widely used in verification, synthesis, and automated reasoning.
• F. None of above. chosen
• G. Unsure - the case is ambiguous/there is not enough information to decide.

Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"

Entity: branching-time temporal logic CTL*
Triple: [E. Allen Emerson, notableWork, branching-time temporal logic CTL*]

Branching-time temporal logic CTL* is a highly expressive formalism in computer science used to specify and reason about the behavior of concurrent and reactive systems over branching time structures.

Target entity: branching-time temporal logic CTL*
Target entity description: Branching-time temporal logic CTL* is a highly expressive formalism in computer science used to specify and reason about the behavior of concurrent and reactive systems over branching time structures.

• A. Temporal Logic of Actions
  Temporal Logic of Actions is a formal framework for specifying and reasoning about concurrent and distributed systems using temporal logic to describe system behaviors over time.
• B. Temporal Verification of Reactive Systems
  "Temporal Verification of Reactive Systems" is a foundational book in formal methods that presents rigorous techniques for specifying and verifying the correctness of reactive and concurrent systems using temporal logic.
• C. Model Checking (book)
  "Model Checking" is a foundational textbook that systematically presents the theory and practice of using automated verification techniques to prove correctness properties of hardware and software systems.
• D. Symbolic Model Checking
  Symbolic Model Checking is a formal verification technique that uses symbolic representations, such as binary decision diagrams, to efficiently verify properties of hardware and software systems with very large state spaces.
• E. Satisfiability Modulo Theories (SMT)
  Satisfiability Modulo Theories (SMT) is a framework in computer science and mathematical logic for deciding the satisfiability of logical formulas with respect to background theories such as arithmetic, bit-vectors, arrays, and data types, widely used in verification, synthesis, and automated reasoning.
• F. None of above. chosen