Triple
T37403356
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Intel Core Ultra |
E929060
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | microprocessor family |
C3600
|
CONCEPT FINISHED |
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69f76ebbf79c8190b85bbcf3a6be57e4 |
completed | May 3, 2026, 3:50 p.m. |
Created at: May 3, 2026, 4:16 p.m.