Triple
T36751978
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | A1200 |
E907937
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | 16/32-bit computer |
C62350
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: 16/32-bit computer Context triple: [A1200, instanceOf, 16/32-bit computer]
-
A.
32-bit computer system
A 32-bit computer system is a computing architecture in which the processor, memory addresses, and data paths are primarily 32 bits wide, defining its data processing capacity and addressable memory range.
-
B.
32-bit operating system
A 32-bit operating system is a software platform that manages computer hardware and software resources using 32-bit wide data paths, memory addresses, and registers, typically supporting up to 4 GB of addressable memory.
-
C.
64-bit processor
A 64-bit processor is a central processing unit (CPU) that processes data and memory addresses in 64-bit chunks, enabling larger addressable memory space and improved performance for compatible software.
-
D.
8-bit computer family
A 8-bit computer family is a group of closely related computer models built around an 8-bit processor architecture, sharing a common instruction set, design philosophy, and often compatible hardware and software ecosystems.
-
E.
8-bit microprocessor
An 8-bit microprocessor is a central processing unit that processes data and instructions in 8-bit chunks, typically featuring an 8-bit data bus and registers, and used in simple computing and embedded systems.
- F. None of above. chosen
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69f76e779bec8190be0e1f87a131e0f4 |
completed | May 3, 2026, 3:49 p.m. |
Created at: May 3, 2026, 4:12 p.m.