Triple
T36643742
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Wilkes microprogramming control |
E904647
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | control-unit design technique |
C62887
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: control-unit design technique Context triple: [Wilkes microprogramming control, instanceOf, control-unit design technique]
-
A.
microprogrammed control unit design
chosen
Microprogrammed control unit design is the method of implementing a processor’s control logic as a sequence of microinstructions stored in control memory, which are fetched and executed to generate the control signals that drive the datapath.
-
B.
RISC architecture
A RISC architecture is a computer processor design that uses a small, highly optimized set of simple instructions to achieve high performance through efficient pipelining and parallelism.
-
C.
selective forwarding unit
A selective forwarding unit is a network component that receives multiple media streams (such as audio or video) and selectively forwards chosen streams or their subsets to different recipients based on criteria like subscription, bandwidth, or layout.
-
D.
bit-level parallelism technique
A bit-level parallelism technique is a method of exploiting the simultaneous processing of multiple bits within a single machine word to accelerate arithmetic and logical operations.
-
E.
architectural unit
An architectural unit is a self-contained, functionally cohesive component of a building or spatial design that serves a specific purpose within the overall architectural system.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69f76e6d3a3c81909db73eda9e0516bd |
completed | May 3, 2026, 3:49 p.m. |
Created at: May 3, 2026, 4:11 p.m.