Triple
T3244624
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | SPARC |
E68040
|
entity |
| Predicate | influencedBy |
P9
|
FINISHED |
| Object |
RISC II
RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
|
E339012
|
NE FINISHED |
Provenance (5 batches)
| Stage | Batch ID | Job type | Status |
|---|---|---|---|
| creating | batch_69ad858e4c708190aa31d486cfee8a6a |
elicitation | completed |
| NER | batch_69adaf1982448190b3d60c9e4471421f |
ner | completed |
| NED1 | batch_69b2775be7c88190ba60b191f1c51e19 |
ned_source_triple | completed |
| NED2 | batch_69b278a64ae48190a00dbeff59ad9d6b |
ned_description | completed |
| NEDg | batch_69b278471ee48190918dd503d1bffd7d |
nedg | completed |
Created at: March 8, 2026, 3:08 p.m.