Triple
T32182811
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | ISE Design Suite |
E822029
|
entity |
| Predicate | optimizedFor |
P98
|
FINISHED |
| Object | Virtex FPGA family |
—
|
NE NERFINISHED |
Provenance (2 batches)
| Stage | Batch ID | Job type | Status |
|---|---|---|---|
| creating | batch_69f3490755288190aee11740a34862f9 |
elicitation | completed |
| NER | batch_69f6baafbbec819098df77476df5ee0d |
ner | completed |
Created at: May 1, 2026, 12:34 a.m.