Triple
T32139427
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | ASIC |
E820861
|
entity |
| Predicate | commonHDL |
P7254
|
FINISHED |
| Object | Verilog |
—
|
NE NERFINISHED |
Provenance (3 batches)
| Stage | Batch ID | Job type | Status |
|---|---|---|---|
| creating | batch_69f349039e0c819091c7a7d322e3f46d |
elicitation | completed |
| NER | batch_69fe38be079c8190a240191ac0e73e3a |
ner | completed |
| PD | batch_69fe350344508190930de2218156ca02 |
pd | completed |
Created at: May 1, 2026, 12:30 a.m.