Triple
T32048094
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | AMD Radeon RX 500 series |
E818405
|
entity |
| Predicate | memoryBusWidthRange |
P178344
|
FINISHED |
| Object | 128-bit to 256-bit |
—
|
LITERAL FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: 128-bit to 256-bit | Statement: [AMD Radeon RX 500 series, memoryBusWidthRange, 128-bit to 256-bit]
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: memoryBusWidthRange Context triple: [AMD Radeon RX 500 series, memoryBusWidthRange, 128-bit to 256-bit]
-
A.
memoryBusWidthBits
chosen
Indicates the width, in bits, of the data path used by the memory bus to transfer information.
-
B.
supportsMemoryBusWidth
Indicates that one entity is compatible with or able to operate using the specified memory bus width of another entity.
-
C.
typicalRAMRange
Indicates the usual or commonly expected range of RAM capacity associated with an entity.
-
D.
busWidthComparedToISA
Indicates how the width of a bus compares to the width defined by a given instruction set architecture (ISA), such as being wider, narrower, or equal.
-
E.
typicalRAMRangeMB
Indicates the usual or expected range of RAM capacity, measured in megabytes, associated with an entity.
- F. None of above.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69f348fcfb648190859f6be5e04b7cfe |
completed | April 30, 2026, 12:20 p.m. |
| NER | Named-entity recognition | batch_69f7221dc9a88190bb8194fcc29c42bc |
completed | May 3, 2026, 10:23 a.m. |
| PD | Predicate disambiguation | batch_69f72153a9188190b02adc84e1be4af8 |
completed | May 3, 2026, 10:20 a.m. |
Created at: May 1, 2026, 12:20 a.m.