Triple
T29391256
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Adafruit Feather M0 boards |
E745373
|
entity |
| Predicate | microcontrollerArchitecture |
P8609
|
FINISHED |
| Object | ARM Cortex-M0+ |
—
|
NE NERFINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: ARM Cortex-M0+ | Statement: [Adafruit Feather M0 boards, microcontrollerArchitecture, ARM Cortex-M0+]
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: microcontrollerArchitecture Context triple: [Adafruit Feather M0 boards, microcontrollerArchitecture, ARM Cortex-M0+]
-
A.
microarchitectureClass
Indicates that one entity is classified as a specific type or category of microarchitecture relative to another entity.
-
B.
graphicsArchitecture
Indicates the underlying design or structural framework that defines how a system’s graphics or visual rendering components are organized and operate.
-
C.
microarchitectureFeature
Indicates a relationship where a specific microarchitecture possesses or supports a particular hardware or design feature.
-
D.
cpuArchitecture
chosen
Indicates the type of processor instruction set or hardware architecture that a computing system or component is designed to run on.
-
E.
hasMicrocontroller
Indicates that an entity contains, includes, or is equipped with a microcontroller as one of its components.
- F. None of above.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69f0a79dfabc81908755382ee47791e2 |
completed | April 28, 2026, 12:27 p.m. |
| NER | Named-entity recognition | batch_69f669ff3b2081909ecfc701841c6532 |
completed | May 2, 2026, 9:17 p.m. |
| PD | Predicate disambiguation | batch_69f66339175c819080bd70f0ff7057b1 |
completed | May 2, 2026, 8:48 p.m. |
Created at: April 28, 2026, 2:42 p.m.