Triple

T29390390
Position Surface form Disambiguated ID Type / Status
Subject UHS-I E745355 entity
Predicate instanceOf P0 FINISHED
Object Ultra High Speed bus standard C163 CONCEPT FINISHED

How this triple was built (1 step)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

CD Concept disambiguation gpt-5-mini-2025-08-07 
Target class: Ultra High Speed bus standard
Context triple: [UHS-I, instanceOf, Ultra High Speed bus standard]
  • A. parallel computer bus
    A parallel computer bus is a communication system that transfers multiple bits of data simultaneously across multiple wires or channels between components within a computer system.
  • B. serial bus interface standard chosen
    A serial bus interface standard defines the electrical, timing, and protocol rules that govern how devices communicate and exchange data over a serial communication bus.
  • C. VMEbus system
    A VMEbus system is a modular computer architecture that uses a shared parallel bus to interconnect processors, memory, and I/O boards in a standardized backplane for industrial and embedded applications.
  • D. 200 Gigabit Ethernet technology
    200 Gigabit Ethernet technology is a high-speed networking standard that delivers 200 gigabits per second of data throughput, enabling faster data center, enterprise, and carrier network performance.
  • E. high-speed transistor
    A high-speed transistor is an electronic switching device designed with materials, structures, and geometries that minimize charge transit time and parasitic effects to enable very fast signal amplification and switching at high frequencies.
  • F. None of above.

Provenance (1 batch)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69f0a79dfabc81908755382ee47791e2 completed April 28, 2026, 12:27 p.m.
Created at: April 28, 2026, 2:41 p.m.