Triple

T29099954
Position Surface form Disambiguated ID Type / Status
Subject Ivory microprocessor E736612 entity
Predicate instanceOf P0 FINISHED
Object Lisp machine CPU C24445 CONCEPT FINISHED

How this triple was built (1 step)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

CD Concept disambiguation gpt-5-mini-2025-08-07
Target class: Lisp machine CPU
Context triple: [Ivory microprocessor, instanceOf, Lisp machine CPU]
  • A. Lisp machine chosen
    A Lisp machine is a specialized computer system designed to efficiently run the Lisp programming language, featuring hardware and software tightly integrated around Lisp’s execution model.
  • B. RISC workstation family
    A RISC workstation family is a series of high-performance desktop or server computers built around Reduced Instruction Set Computing processors, designed for technical, scientific, or engineering applications requiring efficient computation and advanced graphics.
  • C. S-100 bus computer
    An S-100 bus computer is a microcomputer system built around the S-100 expansion bus standard, using a backplane and plug-in cards for CPU, memory, and I/O to create a modular, expandable architecture.
  • D. PDP series computer
    A PDP series computer is a family of minicomputers produced by Digital Equipment Corporation (DEC) from the 1960s to 1980s, known for their relatively low cost, interactive use, and significant influence on computer architecture and operating systems.
  • E. Oberon-family operating system
    An Oberon-family operating system is a minimalist, modular, and tightly integrated system built around the Oberon programming language, combining the OS, runtime, and user interface into a cohesive, extensible environment.
  • F. None of above.

Provenance (1 batch)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69f077ec765c81909474c88bcc8bab43 completed April 28, 2026, 9:03 a.m.
Created at: April 28, 2026, 11:11 a.m.