Triple
T28608066
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | R3000 |
E724105
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | MIPS processor |
C43371
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: MIPS processor Context triple: [R3000, instanceOf, MIPS processor]
-
A.
NS32000 family processor
The NS32000 family processor is a series of 32-bit CISC microprocessors by National Semiconductor, designed with a clean, orthogonal instruction set and advanced features for high-level language support and multitasking.
-
B.
Motorola 88000 family microprocessor
The Motorola 88000 family microprocessor is a series of 32-bit RISC CPUs developed by Motorola in the late 1980s, designed for high-performance computing and embedded systems with a clean, load-store architecture.
-
C.
RISC architecture
A RISC architecture is a computer processor design that uses a small, highly optimized set of simple instructions to achieve high performance through efficient pipelining and parallelism.
-
D.
32-bit RISC processor core
chosen
A 32-bit RISC processor core is a compact, efficient central processing unit design that executes a streamlined set of fixed-size instructions on 32-bit data and addresses to optimize performance, power, and implementation simplicity.
-
E.
Motorola 680x0 family processor
A Motorola 680x0 family processor is a 32-bit CISC microprocessor architecture used in many 1980s–1990s computers and workstations, known for its orthogonal instruction set and influential role in systems like the Apple Macintosh, Amiga, and Atari ST.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69f01d816d7c8190a1fe27e3434041dc |
completed | April 28, 2026, 2:37 a.m. |
Created at: April 28, 2026, 4:28 a.m.