Triple
T27866189
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | PDP-9 |
E704365
|
entity |
| Predicate | cpuTechnology |
P163426
|
FINISHED |
| Object | discrete transistor logic |
—
|
LITERAL FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: discrete transistor logic | Statement: [PDP-9, cpuTechnology, discrete transistor logic]
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: cpuTechnology Context triple: [PDP-9, cpuTechnology, discrete transistor logic]
-
A.
cpuImplementation
Indicates that one entity serves as the hardware or architectural realization (implementation) of a specified CPU design or model.
-
B.
cpuCoreMicroarchitecture
Indicates the specific microarchitecture design implemented in a given CPU core.
-
C.
microarchitectureGeneration
Indicates the specific microarchitecture design generation or family to which a processor or hardware component belongs.
-
D.
microarchitectureFeature
Indicates a relationship where a specific microarchitecture possesses or supports a particular hardware or design feature.
-
E.
cpuArchitecture
Indicates the type of processor instruction set or hardware architecture that a computing system or component is designed to run on.
- F. None of above. chosen
Provenance (4 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ef840f12408190b539d00d79658abf |
completed | April 27, 2026, 3:43 p.m. |
| NER | Named-entity recognition | batch_69f6394830f88190addc152141c50b78 |
completed | May 2, 2026, 5:50 p.m. |
| PD | Predicate disambiguation | batch_69f6318ae6f08190b3f85f9201046a15 |
completed | May 2, 2026, 5:16 p.m. |
| PDg | Predicate description generation | batch_69f6359d46b88190922dd7de508e3b0e |
completed | May 2, 2026, 5:34 p.m. |
Created at: April 27, 2026, 6:21 p.m.