Triple
T25931874
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Intel SHA Extensions |
E653455
|
entity |
| Predicate | CPUIDLeaf |
P158289
|
FINISHED |
| Object | 0x07 |
—
|
LITERAL FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: 0x07 | Statement: [Intel SHA Extensions, CPUIDLeaf, 0x07]
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: CPUIDLeaf Context triple: [Intel SHA Extensions, CPUIDLeaf, 0x07]
-
A.
cpuidLeaf
chosen
Indicates the specific CPUID instruction leaf or subfunction being referenced in a processor identification query.
-
B.
cpuidRegisterBit
Indicates that a specific bit within a given CPU ID (CPUID) register has a particular state or property relevant to the processor’s capabilities or features.
-
C.
CPUCoreConfiguration
Indicates the specific arrangement and characteristics of processor cores allocated or defined within a computing system.
-
D.
cpuImplementation
Indicates that one entity serves as the hardware or architectural realization (implementation) of a specified CPU design or model.
-
E.
cpuCoreMicroarchitecture
Indicates the specific microarchitecture design implemented in a given CPU core.
- F. None of above.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e7ab3eb9b881909c1390690551f868 |
completed | April 21, 2026, 4:52 p.m. |
| NER | Named-entity recognition | batch_69f604192b6c8190b86e151a628eafd8 |
completed | May 2, 2026, 2:03 p.m. |
| PD | Predicate disambiguation | batch_69f5afec3e94819080d9ba86cf8c866e |
completed | May 2, 2026, 8:03 a.m. |
Created at: April 22, 2026, 8:37 a.m.