Triple
T25425941
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Intel 430FX chipset |
E637114
|
entity |
| Predicate | supportsDRAMRefresh |
P178747
|
FINISHED |
| Object | hidden refresh |
—
|
LITERAL FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: hidden refresh | Statement: [Intel 430FX chipset, supportsDRAMRefresh, hidden refresh]
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: supportsDRAMRefresh Context triple: [Intel 430FX chipset, supportsDRAMRefresh, hidden refresh]
-
A.
supportsLPDDR4Memory
Indicates that an entity is compatible with and can operate using LPDDR4 memory technology.
-
B.
supportsLPDDR4XMemory
Indicates that an entity is compatible with and can operate using LPDDR4X memory modules.
-
C.
supportsVariableRefreshRate
Indicates that one entity provides compatibility with or functionality for dynamically adjusting refresh rates in coordination with another entity.
-
D.
hasRAM
Indicates that an entity possesses or is equipped with a specified amount or type of random-access memory (RAM).
-
E.
supportsMemoryParity
Indicates that one entity provides or enables memory parity protection or compatibility for another entity’s memory operations.
- F. None of above. chosen
Provenance (4 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e75db58a1c8190891b9ff7c2f8414e |
completed | April 21, 2026, 11:21 a.m. |
| NER | Named-entity recognition | batch_69f71422adac8190a5ceb32dcf820833 |
completed | May 3, 2026, 9:23 a.m. |
| PD | Predicate disambiguation | batch_69f712764d2c819081b64b27e5de4a13 |
completed | May 3, 2026, 9:16 a.m. |
| PDg | Predicate description generation | batch_69f71421e8d08190807ccfb15d0f0ddb |
completed | May 3, 2026, 9:23 a.m. |
Created at: April 21, 2026, 1:57 p.m.