Triple
T25425783
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Intel Pentium II |
E637111
|
entity |
| Predicate | L2CacheSpeedRelation |
P158830
|
FINISHED |
| Object | half core clock speed |
—
|
LITERAL FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: half core clock speed | Statement: [Intel Pentium II, L2CacheSpeedRelation, half core clock speed]
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: L2CacheSpeedRelation Context triple: [Intel Pentium II, L2CacheSpeedRelation, half core clock speed]
-
A.
L2CacheAssociativity
Indicates how many distinct cache lines in the L2 cache can map to the same memory address set, defining the degree of parallel placement for data in that cache level.
-
B.
L2Cache
Indicates that one entity functions as a level-2 cache for another, storing intermediate data or results to speed up repeated access or computation.
-
C.
l2CacheType
Indicates the specific configuration or design category of an entity’s level-2 (L2) cache in a memory hierarchy.
-
D.
l2CacheTypicalSize
Indicates the typical or standard size of an entity’s level-2 (L2) cache in a computing system.
-
E.
L2CacheBusWidth
Indicates the width of the data bus used to connect to the Level 2 (L2) cache, typically measured in bits.
- F. None of above. chosen
Provenance (4 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e75db58a1c8190891b9ff7c2f8414e |
completed | April 21, 2026, 11:21 a.m. |
| NER | Named-entity recognition | batch_69f5f6bfdb748190abfd40ed1838d9aa |
completed | May 2, 2026, 1:06 p.m. |
| PD | Predicate disambiguation | batch_69f4806d93dc8190b9dff4c63186faff |
completed | May 1, 2026, 10:29 a.m. |
| PDg | Predicate description generation | batch_69f48b9058d081908ec9af261ee092e2 |
completed | May 1, 2026, 11:16 a.m. |
Created at: April 21, 2026, 1:57 p.m.