Triple
T23259101
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | WASI component model |
E581954
|
entity |
| Predicate | designedBy |
P184
|
FINISHED |
| Object | Bytecode Alliance |
—
|
NE NERFINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Bytecode Alliance | Statement: [WASI component model, designedBy, Bytecode Alliance]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Bytecode Alliance Context triple: [WASI component model, designedBy, Bytecode Alliance]
-
A.
Bytecode Alliance
chosen
Bytecode Alliance is a nonprofit industry consortium focused on advancing secure, modular, and portable software through technologies built around WebAssembly.
-
B.
RISC-V International
RISC-V International is the global nonprofit consortium that oversees the development, standardization, and promotion of the open RISC-V instruction set architecture.
-
C.
Zig Software Foundation
The Zig Software Foundation is the organization responsible for stewarding the development, ecosystem, and community of the Zig programming language.
-
D.
LLVM
LLVM is a modular, reusable compiler and toolchain infrastructure project widely used for building language frontends, optimizers, and backends for diverse hardware architectures.
-
E.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (2 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e246079f58819085eaa9c260906880 |
completed | April 17, 2026, 2:39 p.m. |
| NER | Named-entity recognition | batch_69f194c710c48190aff03d210642a043 |
completed | April 29, 2026, 5:19 a.m. |
Created at: April 17, 2026, 4:11 p.m.