Triple
T22552248
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | John Cocke |
E557586
|
entity |
| Predicate | notableWork |
P4
|
FINISHED |
| Object | RISC architecture |
—
|
NE NERFINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: RISC architecture | Statement: [John Cocke, notableWork, RISC architecture]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: RISC architecture Context triple: [John Cocke, notableWork, RISC architecture]
-
A.
RISC architecture
chosen
RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
-
B.
RISC
RISC is an Austrian research institute specializing in symbolic computation, computer algebra, and related areas of mathematics and computer science.
-
C.
Precision Architecture – Reduced Instruction Set Computing
Precision Architecture – Reduced Instruction Set Computing (PA-RISC) is Hewlett-Packard’s proprietary RISC microprocessor architecture designed to deliver high performance and efficiency in HP workstations and servers.
-
D.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
E.
Harvard architecture
Harvard architecture is a computer architecture design that uses separate memory and signal pathways for instructions and data, enabling simultaneous access and often improved performance over unified-memory designs.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (2 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e11e59db848190b4272ecd2b690ffd |
completed | April 16, 2026, 5:37 p.m. |
| NER | Named-entity recognition | batch_69f15f7647208190a1aaebd083bf095a |
completed | April 29, 2026, 1:31 a.m. |
Created at: April 16, 2026, 8:52 p.m.