Triple

T22445402
Position Surface form Disambiguated ID Type / Status
Subject R^nRS E554850 entity
Predicate relatedTo P37 FINISHED
Object IEEE Scheme standard NE NERFINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: IEEE Scheme standard | Statement: [R^nRS, relatedTo, IEEE Scheme standard]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: IEEE Scheme standard
Context triple: [R^nRS, relatedTo, IEEE Scheme standard]
  • A. IEEE Scheme chosen
    IEEE Scheme is a standardized subset of the Scheme programming language defined by the IEEE to ensure portability and consistency across Scheme implementations.
  • B. IEEE standards
    IEEE standards are globally recognized technical guidelines and specifications developed by the Institute of Electrical and Electronics Engineers to ensure interoperability, safety, and quality across a wide range of electrical, electronic, and computing technologies.
  • C. IEEE 1364
    IEEE 1364 is the IEEE standard that defines the Verilog hardware description language used for modeling and designing digital electronic systems.
  • D. IEEE Standard for High-Speed Test Access Port and Boundary-Scan Architecture
    IEEE 1149.10 is a JTAG-related IEEE standard that defines a high-speed test access and boundary-scan architecture for efficient testing and debugging of complex digital integrated circuits and systems.
  • E. IEEE 1149 family of standards
    The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (2 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69e11e5113208190ab58c6b595f9d1d0 completed April 16, 2026, 5:37 p.m.
NER Named-entity recognition batch_69f15b46e8ac8190bfa8c611ffcba822 completed April 29, 2026, 1:13 a.m.
Created at: April 16, 2026, 8:47 p.m.