Triple
T21007870
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | MIPS R5000 |
E517460
|
entity |
| Predicate | architectureFamily |
P8152
|
FINISHED |
| Object | MIPS |
—
|
NE NERFINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS | Statement: [MIPS R5000, architectureFamily, MIPS]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS Context triple: [MIPS R5000, architectureFamily, MIPS]
-
A.
MIPS
MIPS is an infrared imaging and photometry instrument that operated aboard the Spitzer Space Telescope, used to study celestial objects at multiple mid- to far-infrared wavelengths.
-
B.
MIPS
chosen
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
C.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
-
D.
MIPS III
MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
-
E.
MIPS R2000
The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (2 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e0b50192308190a284fcc89dd23a49 |
completed | April 16, 2026, 10:08 a.m. |
| NER | Named-entity recognition | batch_69e6fc3cc8648190b1a419ef734a69e6 |
completed | April 21, 2026, 4:25 a.m. |
Created at: April 16, 2026, 1:53 p.m.