Triple
T20989497
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | AN/APS-125 |
E516979
|
entity |
| Predicate | typeDesignationSystem |
P19205
|
FINISHED |
| Object | Joint Electronics Type Designation System (JETDS) |
—
|
NE NERFINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Joint Electronics Type Designation System (JETDS) | Statement: [AN/APS-125, typeDesignationSystem, Joint Electronics Type Designation System (JETDS)]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Joint Electronics Type Designation System (JETDS) Context triple: [AN/APS-125, typeDesignationSystem, Joint Electronics Type Designation System (JETDS)]
-
A.
Joint Electronics Type Designation System
chosen
The Joint Electronics Type Designation System is a standardized U.S. military naming convention used to classify and identify electronic equipment such as radars, radios, and sensors across the armed services.
-
B.
IEEE 1149.1 JTAG boundary‑scan standard
The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
-
C.
EIA-449
EIA-449 is a telecommunications standard that defines electrical and mechanical interface characteristics for high-speed serial data communication between data terminal equipment and data circuit-terminating equipment.
-
D.
JEDEC standards
JEDEC standards are industry-wide technical specifications that define the design, operation, and interoperability of semiconductor memory and related electronic components.
-
E.
IEEE 1149 family of standards
The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (2 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e0b4ffac148190bbade9f0eceb660b |
completed | April 16, 2026, 10:07 a.m. |
| NER | Named-entity recognition | batch_69e6fbe5f49c8190a5c031eceba9ebf7 |
completed | April 21, 2026, 4:24 a.m. |
Created at: April 16, 2026, 1:49 p.m.