Triple

T20906015
Position Surface form Disambiguated ID Type / Status
Subject MIPS R4600 E514800 entity
Predicate floatingPointCoprocessor P86810 FINISHED
Object MIPS R4010 NE NERFINISHED

How this triple was built (3 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS R4010 | Statement: [MIPS R4600, floatingPointCoprocessor, MIPS R4010]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: MIPS R4010
Context triple: [MIPS R4600, floatingPointCoprocessor, MIPS R4010]
  • A. MIPS R4600
    The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
  • B. MIPS R5000
    The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
  • C. MIPS R2000
    The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.
  • D. MIPS R3000
    The MIPS R3000 is a 32-bit RISC microprocessor widely used in late-1980s and early-1990s workstations, servers, and embedded systems.
  • E. R4000 chosen
    The R4000 is a 64-bit MIPS microprocessor that introduced a new generation of high-performance, RISC-based CPU designs widely used in workstations and servers in the early 1990s.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
PD Predicate disambiguation gpt-5-mini-2025-08-07
Target predicate: floatingPointCoprocessor
Context triple: [MIPS R4600, floatingPointCoprocessor, MIPS R4010]
  • A. floatingPointPerformance
    Indicates the level of computational capability or efficiency an entity has when performing floating-point arithmetic operations.
  • B. floatingPointRegisterCount
    Indicates the number of floating-point registers associated with an entity (such as a processor or execution context).
  • C. numberOfFloatingPointUnits
    Indicates the quantity of floating-point processing units associated with or contained in an entity.
  • D. FPU chosen
    Indicates that one entity functions as or contains a floating-point unit responsible for performing arithmetic operations on non-integer (floating-point) numbers for another entity or within a system.
  • E. floatingPointUnitSharing
    Indicates that two or more processing units share access to a common floating-point execution resource rather than each having a dedicated one.
  • F. None of above.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69e0b4f8a1108190bce3d31331290ced completed April 16, 2026, 10:07 a.m.
NER Named-entity recognition batch_69e6e9001a8c81909fa1004b5977d04f completed April 21, 2026, 3:03 a.m.
PD Predicate disambiguation batch_69e5c9ac91108190a6700fcdf2f11890 completed April 20, 2026, 6:37 a.m.
Created at: April 16, 2026, 12:47 p.m.