Triple
T19451562
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Apple A10 Fusion |
E486623
|
entity |
| Predicate | supports |
P516
|
FINISHED |
| Object | ARM NEON |
—
|
NE NERFINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: ARM NEON | Statement: [Apple A10 Fusion, supports, ARM NEON]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: ARM NEON Context triple: [Apple A10 Fusion, supports, ARM NEON]
-
A.
NEON SIMD
chosen
NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
-
B.
ARM SVE
ARM SVE (Scalable Vector Extension) is an ARM architecture extension that provides flexible, length-agnostic vector processing capabilities aimed at high-performance computing and data-intensive workloads.
-
C.
V (vector extension)
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
-
D.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
-
E.
ARMv8-A
ARMv8-A is a 64-bit ARM processor architecture generation that introduces the AArch64 execution state and underpins many modern mobile and desktop CPUs.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (2 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d8e8d7ad488190a3373045029b0f3b |
completed | April 10, 2026, 12:11 p.m. |
| NER | Named-entity recognition | batch_69e63392aab08190aab09b7c356e5b10 |
completed | April 20, 2026, 2:09 p.m. |
Created at: April 10, 2026, 1:38 p.m.