Triple

T18591401
Position Surface form Disambiguated ID Type / Status
Subject ICL 1900 series E454376 entity
Predicate basedOn P98 FINISHED
Object ICT 1900 architecture NE NERFINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: ICT 1900 architecture | Statement: [ICL 1900 series, basedOn, ICT 1900 architecture]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: ICT 1900 architecture
Context triple: [ICL 1900 series, basedOn, ICT 1900 architecture]
  • A. ICT 1900 series chosen
    The ICT 1900 series was a family of mainframe computers introduced in the 1960s that became widely used in British and European commercial and scientific computing.
  • B. ICT 1500 series
    The ICT 1500 series was a line of early electronic computers produced by International Computers and Tabulators that played a role in the transition from electromechanical to fully electronic data processing in the mid-20th century.
  • C. Alpha architecture
    Alpha architecture is a 64-bit RISC microprocessor architecture known for its high performance and use in workstations and servers in the 1990s and early 2000s.
  • D. S9 Architecture
    S9 Architecture is a New York–based design firm known for large-scale urban waterfront and mixed-use developments, including major projects like The Wharf in Washington, D.C.
  • E. POWER Architecture, first generation
    POWER Architecture, first generation refers to IBM’s original POWER1 RISC microprocessor design that formed the basis for the later POWER and PowerPC processor families.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (2 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69d8d38ae7e081908a98df1251842402 completed April 10, 2026, 10:40 a.m.
NER Named-entity recognition batch_69e545b5bc688190bdfe3911ac6b2d76 completed April 19, 2026, 9:14 p.m.
Created at: April 10, 2026, 11:44 a.m.