Triple
T18294082
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | EIA-449 |
E438185
|
entity |
| Predicate | replacedBy |
P101
|
FINISHED |
| Object | EIA-530 |
—
|
NE NERFINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: EIA-530 | Statement: [EIA-449, replacedBy, EIA-530]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: EIA-530 Context triple: [EIA-449, replacedBy, EIA-530]
-
A.
EIA-449
chosen
EIA-449 is a telecommunications standard that defines electrical and mechanical interface characteristics for high-speed serial data communication between data terminal equipment and data circuit-terminating equipment.
-
B.
IEEE 1355
IEEE 1355 is a high-speed serial interconnect standard designed for simple, low-latency, and scalable communication between electronic systems.
-
C.
EIA-232
EIA-232 is a standard for serial binary data communication that defines electrical and signaling characteristics for connecting data terminal equipment and data communication equipment.
-
D.
IEEE 1532
IEEE 1532 is an extension of the JTAG boundary-scan standard that defines in-system programming and configuration procedures for programmable devices such as FPGAs and CPLDs.
-
E.
IEEE 1500
IEEE 1500 is an IEEE standard that defines a modular test architecture for embedded cores within system-on-chip (SoC) designs to facilitate efficient and standardized core-level testing.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (2 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d8b915e3e881909125d760c15d0c29 |
completed | April 10, 2026, 8:47 a.m. |
| NER | Named-entity recognition | batch_69e5010205bc8190a32fe731ead3d988 |
completed | April 19, 2026, 4:21 p.m. |
Created at: April 10, 2026, 10:35 a.m.