Triple

T1775192
Position Surface form Disambiguated ID Type / Status
Subject Icestorm E38960 entity
Predicate supports P516 FINISHED
Object NEON SIMD
NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
E198707 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: NEON SIMD | Statement: [Icestorm, supports, NEON SIMD]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: NEON SIMD
Context triple: [Icestorm, supports, NEON SIMD]
  • A. V (vector extension)
    V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • B. P (packed-SIMD extension)
    P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
  • C. SSSE3
    SSSE3 (Supplemental Streaming SIMD Extensions 3) is an Intel SIMD instruction set extension that enhances performance for multimedia, signal processing, and other parallelizable workloads.
  • D. Intel AVX2
    Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
  • E. AltiVec
    AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: NEON SIMD
Triple: [Icestorm, supports, NEON SIMD]
Generated description
NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: NEON SIMD
Target entity description: NEON SIMD is ARM's advanced Single Instruction, Multiple Data (SIMD) instruction set extension designed to accelerate multimedia, signal processing, and other parallelizable workloads on ARM processors.
  • A. V (vector extension)
    V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • B. P (packed-SIMD extension)
    P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
  • C. SSSE3
    SSSE3 (Supplemental Streaming SIMD Extensions 3) is an Intel SIMD instruction set extension that enhances performance for multimedia, signal processing, and other parallelizable workloads.
  • D. Intel AVX2
    Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
  • E. AltiVec
    AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69a8862e61708190af97b9838cc3f5de completed March 4, 2026, 7:21 p.m.
NER Named-entity recognition batch_69aa64b6c4a88190ab2f75c8d4814f11 completed March 6, 2026, 5:23 a.m.
NED1 Entity disambiguation (via context triple) batch_69ada9982d208190b0c29ee1141e91b0 completed March 8, 2026, 4:53 p.m.
NEDg Description generation batch_69adab03a5448190b42966adcd8afbde completed March 8, 2026, 4:59 p.m.
NED2 Entity disambiguation (via description) batch_69adaeabff6c8190b19bc6478a28641c completed March 8, 2026, 5:15 p.m.
Created at: March 4, 2026, 7:31 p.m.