Triple

T1429500
Position Surface form Disambiguated ID Type / Status
Subject Intel Atom E30411 entity
Predicate supports P516 FINISHED
Object SSE2
SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
 E163309 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: SSE2 | Statement: [Intel Atom, supports, SSE2]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: SSE2
Context triple: [Intel Atom, supports, SSE2]
  • A. AltiVec
    AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
  • B. AMD64 architecture
    The AMD64 architecture is a 64-bit instruction set architecture introduced by AMD that extends the x86 design to support larger memory addressing and enhanced performance while maintaining backward compatibility with 32-bit software.
  • C. Intel Xeon
    Intel Xeon is a family of high-performance x86 processors designed by Intel for servers, workstations, and data center applications requiring reliability, scalability, and advanced multi-core processing.
  • D. AMD processors
    AMD processors are a family of CPUs and APUs from Advanced Micro Devices known for offering strong multi-core performance and competitive pricing across desktops, laptops, and mobile devices.
  • E. SPARC microprocessor architecture
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: SSE2
Triple: [Intel Atom, supports, SSE2]
Generated description
SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07 
Target entity: SSE2
Target entity description: SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
  • A. AltiVec
    AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
  • B. AMD64 architecture
    The AMD64 architecture is a 64-bit instruction set architecture introduced by AMD that extends the x86 design to support larger memory addressing and enhanced performance while maintaining backward compatibility with 32-bit software.
  • C. Intel Xeon
    Intel Xeon is a family of high-performance x86 processors designed by Intel for servers, workstations, and data center applications requiring reliability, scalability, and advanced multi-core processing.
  • D. AMD processors
    AMD processors are a family of CPUs and APUs from Advanced Micro Devices known for offering strong multi-core performance and competitive pricing across desktops, laptops, and mobile devices.
  • E. SPARC microprocessor architecture
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69a498fc69ec8190b61722bd4b67c4d2 completed March 1, 2026, 7:52 p.m.
NER Named-entity recognition batch_69a4c4db2d7481908d241593d0e17d83 completed March 1, 2026, 10:59 p.m.
NED1 Entity disambiguation (via context triple) batch_69ad016930ec8190ab3900d6f40c4aa0 completed March 8, 2026, 4:56 a.m.
NEDg Description generation batch_69ad01d1c01c81908917c4837ed2b393 completed March 8, 2026, 4:57 a.m.
NED2 Entity disambiguation (via description) batch_69ad0265f610819085a2dd293abd4812 completed March 8, 2026, 5 a.m.
Created at: March 1, 2026, 8 p.m.