Triple

T14086542
Position Surface form Disambiguated ID Type / Status
Subject SPARC International E339010 entity
Predicate relatedStandard P37 FINISHED
Object SPARC V8 E68040 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: SPARC V8 | Statement: [SPARC International, relatedStandard, SPARC V8]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: SPARC V8
Context triple: [SPARC International, relatedStandard, SPARC V8]
  • A. SPARC microprocessor architecture chosen
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • B. MIPS R5000
    The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
  • C. MIPS R2000
    The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.
  • D. MIPS R4600
    The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
  • E. Hitachi SH-4
    The Hitachi SH-4 is a 32-bit RISC microprocessor known for its use in late-1990s gaming consoles and embedded systems, featuring strong floating-point performance for 3D graphics.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69d81c687b0c819087fd9ed4198403f8 completed April 9, 2026, 9:38 p.m.
NER Named-entity recognition batch_69de5edff1b881909ea56dc2429ef2dd completed April 14, 2026, 3:36 p.m.
NED1 Entity disambiguation (via context triple) batch_69fcd0a3e55c81909b52f618e9076dd2 completed May 7, 2026, 5:49 p.m.
Created at: April 9, 2026, 10:21 p.m.