Triple
T13319914
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | SOIC-8 |
E317286
|
entity |
| Predicate | hasStandard |
P1371
|
FINISHED |
| Object | JEDEC MO-150 |
E739489
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: JEDEC MO-150 | Statement: [SOIC-8, hasStandard, JEDEC MO-150]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: JEDEC MO-150 Context triple: [SOIC-8, hasStandard, JEDEC MO-150]
-
A.
JEDEC standards
chosen
JEDEC standards are industry-wide technical specifications that define the design, operation, and interoperability of semiconductor memory and related electronic components.
-
B.
IEEE 1149.6
IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
-
C.
IEEE 1500
IEEE 1500 is an IEEE standard that defines a modular test architecture for embedded cores within system-on-chip (SoC) designs to facilitate efficient and standardized core-level testing.
-
D.
IEEE 1149.4
IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
-
E.
IEEE 1532
IEEE 1532 is an extension of the JTAG boundary-scan standard that defines in-system programming and configuration procedures for programmable devices such as FPGAs and CPLDs.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d806b4d62c81908d4ced1665414be5 |
completed | April 9, 2026, 8:06 p.m. |
| NER | Named-entity recognition | batch_69d990faa95481908a7fd297959c062e |
completed | April 11, 2026, 12:08 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69f716ee695c81909ffeeb0901ee66c1 |
completed | May 3, 2026, 9:35 a.m. |
Created at: April 9, 2026, 9:29 p.m.