Triple
T12562686
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Ingres Corporation |
E295387
|
entity |
| Predicate | hasProgrammingLanguageSupport |
P83124
|
FINISHED |
| Object | OpenROAD 4GL |
E991188
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: OpenROAD 4GL | Statement: [Ingres Corporation, hasProgrammingLanguageSupport, OpenROAD 4GL]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: OpenROAD 4GL Context triple: [Ingres Corporation, hasProgrammingLanguageSupport, OpenROAD 4GL]
-
A.
OpenROAD
chosen
OpenROAD is a fourth-generation application development and deployment environment created by Ingres Corporation for building database-centric client/server and web applications.
-
B.
Altera Hardware Description Language
Altera Hardware Description Language (AHDL) is a proprietary hardware description language developed by Altera for designing and implementing digital logic circuits on its programmable logic devices.
-
C.
Artix FPGA family
The Artix FPGA family is a series of low-cost, low-power field-programmable gate arrays from Xilinx designed for high-performance, cost-sensitive applications such as communications, industrial, and consumer electronics.
-
D.
Tessent
Tessent is a suite of design-for-test and yield analysis tools from Mentor Graphics (now Siemens EDA) used to improve the testability and reliability of integrated circuits.
-
E.
IEEE 1364
IEEE 1364 is the IEEE standard that defines the Verilog hardware description language used for modeling and designing digital electronic systems.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d6ad9cac2c81908e8a7bed82d1e21d |
completed | April 8, 2026, 7:33 p.m. |
| NER | Named-entity recognition | batch_69d95494ae1c81908b9ee14b8ef92a65 |
completed | April 10, 2026, 7:50 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69f65eb71c548190826d243a354bd01c |
completed | May 2, 2026, 8:29 p.m. |
Created at: April 8, 2026, 11:48 p.m.