Triple
T12514705
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | GNU As |
E299165
|
entity |
| Predicate | supportsTarget |
P5090
|
FINISHED |
| Object |
C-SKY
C-SKY is a family of 32-bit embedded processor architectures developed in China, commonly used in low-power and cost-sensitive applications.
|
E986961
|
NE FINISHED |
How this triple was built (4 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: C-SKY | Statement: [GNU As, supportsTarget, C-SKY]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: C-SKY Context triple: [GNU As, supportsTarget, C-SKY]
-
A.
HiSilicon Kirin 64-bit SoCs
HiSilicon Kirin 64-bit SoCs are a family of smartphone and tablet processors developed by Huawei’s semiconductor division, featuring modern 64-bit ARM-based CPU architectures and integrated mobile connectivity.
-
B.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
C.
Tensilica Xtensa LX6
Tensilica Xtensa LX6 is a customizable 32-bit RISC processor core widely used in embedded systems for its efficient performance and low power consumption, notably in Espressif’s ESP32 SoCs.
-
D.
Nios II
Nios II is a soft-core 32-bit RISC processor architecture developed by Altera (now Intel) for implementation on FPGA devices.
-
E.
Hitachi SH-4
The Hitachi SH-4 is a 32-bit RISC microprocessor known for its use in late-1990s gaming consoles and embedded systems, featuring strong floating-point performance for 3D graphics.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: C-SKY Triple: [GNU As, supportsTarget, C-SKY]
Generated description
C-SKY is a family of 32-bit embedded processor architectures developed in China, commonly used in low-power and cost-sensitive applications.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: C-SKY Target entity description: C-SKY is a family of 32-bit embedded processor architectures developed in China, commonly used in low-power and cost-sensitive applications.
-
A.
HiSilicon Kirin 64-bit SoCs
HiSilicon Kirin 64-bit SoCs are a family of smartphone and tablet processors developed by Huawei’s semiconductor division, featuring modern 64-bit ARM-based CPU architectures and integrated mobile connectivity.
-
B.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
C.
Tensilica Xtensa LX6
Tensilica Xtensa LX6 is a customizable 32-bit RISC processor core widely used in embedded systems for its efficient performance and low power consumption, notably in Espressif’s ESP32 SoCs.
-
D.
Nios II
Nios II is a soft-core 32-bit RISC processor architecture developed by Altera (now Intel) for implementation on FPGA devices.
-
E.
Hitachi SH-4
The Hitachi SH-4 is a 32-bit RISC microprocessor known for its use in late-1990s gaming consoles and embedded systems, featuring strong floating-point performance for 3D graphics.
- F. None of above. chosen
Provenance (5 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d6ada5cdd48190860d9ce30aff69be |
completed | April 8, 2026, 7:33 p.m. |
| NER | Named-entity recognition | batch_69d9541e752c8190bf12d2b5a37b53df |
completed | April 10, 2026, 7:48 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69f64bbd58b88190baeb99380babf64f |
completed | May 2, 2026, 7:08 p.m. |
| NEDg | Description generation | batch_69f64ce1b0ec8190bcbd245255e548b5 |
completed | May 2, 2026, 7:13 p.m. |
| NED2 | Entity disambiguation (via description) | batch_69f64da735f48190b051ce173c13e5b2 |
completed | May 2, 2026, 7:16 p.m. |
Created at: April 8, 2026, 9:57 p.m.