Triple

T11946660
Position Surface form Disambiguated ID Type / Status
Subject HP PA-RISC E284315 entity
Predicate abbreviation P43 FINISHED
Object PA-RISC E284315 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: PA-RISC | Statement: [HP PA-RISC, abbreviation, PA-RISC]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: PA-RISC
Context triple: [HP PA-RISC, abbreviation, PA-RISC]
  • A. HP PA-RISC chosen
    HP PA-RISC is a reduced instruction set computer (RISC) microprocessor architecture developed by Hewlett-Packard for use in its workstations and servers.
  • B. DEC Alpha
    DEC Alpha is a 64-bit RISC microprocessor architecture developed by Digital Equipment Corporation in the early 1990s, known for its high performance and use in workstations and servers.
  • C. Risc PC
    Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
  • D. Acorn RISC Machine
    Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
  • E. DEC Alpha 21164
    The DEC Alpha 21164 is a 64-bit RISC microprocessor from Digital Equipment Corporation’s Alpha family, known for its high performance and use in advanced workstations and servers in the mid-1990s.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69d6ab2db38c8190b1f0ed6663ef8ada completed April 8, 2026, 7:23 p.m.
NER Named-entity recognition batch_69d903456ec0819082b8b10755a6b732 completed April 10, 2026, 2:03 p.m.
NED1 Entity disambiguation (via context triple) batch_69f458cbb08881909a71f0592c9231ae completed May 1, 2026, 7:39 a.m.
Created at: April 8, 2026, 9:45 p.m.