Triple
T11305630
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | PCI-X |
E267705
|
entity |
| Predicate | version |
P3286
|
FINISHED |
| Object | PCI-X 1.0 |
E267705
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: PCI-X 1.0 | Statement: [PCI-X, version, PCI-X 1.0]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: PCI-X 1.0 Context triple: [PCI-X, version, PCI-X 1.0]
-
A.
PCI-X
chosen
PCI-X is an older high-speed parallel computer expansion bus standard used mainly in servers and workstations before being superseded by PCI Express.
-
B.
PCI bus
The PCI bus is a widely adopted computer expansion bus standard that provides a high-speed, processor-independent interface for connecting peripheral devices to a motherboard.
-
C.
PCI Express
PCI Express is a high-speed serial computer expansion bus standard used to connect components like graphics cards, SSDs, and network cards to a motherboard.
-
D.
VESA Local Bus
VESA Local Bus was a high-speed expansion bus standard for IBM-compatible PCs in the early 1990s, designed primarily to improve graphics and overall system performance by providing a faster connection to the CPU than the older ISA bus.
-
E.
PCI-SIG
PCI-SIG is an industry consortium that defines and maintains the PCI Express (PCIe) and related peripheral interconnect standards for computers and electronic devices.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d6aaca5c24819083db46a30d86cb34 |
completed | April 8, 2026, 7:21 p.m. |
| NER | Named-entity recognition | batch_69d7e9a7255c81909675fe9ad6d71934 |
completed | April 9, 2026, 6:02 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69e50a62ceec8190af25edf44c5fc1e9 |
completed | April 19, 2026, 5:01 p.m. |
Created at: April 8, 2026, 9:32 p.m.