Triple

T11226561
Position Surface form Disambiguated ID Type / Status
Subject IEEE 1500 embedded core test standard E265710 entity
Predicate fullName P16 FINISHED
Object IEEE Standard Testability Method for Embedded Core-based Integrated Circuits E265710 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: IEEE Standard Testability Method for Embedded Core-based Integrated Circuits | Statement: [IEEE 1500 embedded core test standard, fullName, IEEE Standard Testability Method for Embedded Core-based Integrated Circuits]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: IEEE Standard Testability Method for Embedded Core-based Integrated Circuits
Context triple: [IEEE 1500 embedded core test standard, fullName, IEEE Standard Testability Method for Embedded Core-based Integrated Circuits]
  • A. IEEE 1500 embedded core test standard chosen
    The IEEE 1500 embedded core test standard defines a structured test access and wrapper architecture for testing individual IP cores within system-on-chip (SoC) designs.
  • B. IEEE 1149 family of standards
    The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
  • C. IEEE Standard for High-Speed Test Access Port and Boundary-Scan Architecture
    IEEE 1149.10 is a JTAG-related IEEE standard that defines a high-speed test access and boundary-scan architecture for efficient testing and debugging of complex digital integrated circuits and systems.
  • D. IEEE 1149.1 JTAG boundary‑scan standard
    The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
  • E. IEEE 1149.4
    IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69d6aac656d48190b275efaa7d6074ee completed April 8, 2026, 7:21 p.m.
NER Named-entity recognition batch_69d7e8ff7b40819089c835be710bc575 completed April 9, 2026, 5:59 p.m.
NED1 Entity disambiguation (via context triple) batch_69e4ad33fdf48190a7118c7c30577ec9 completed April 19, 2026, 10:23 a.m.
Created at: April 8, 2026, 9:30 p.m.