Triple
T11146197
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | IRS-1C |
E263674
|
entity |
| Predicate | spacecraftBus |
P12569
|
FINISHED |
| Object | IRS-1 bus |
E898967
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: IRS-1 bus | Statement: [IRS-1C, spacecraftBus, IRS-1 bus]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: IRS-1 bus Context triple: [IRS-1C, spacecraftBus, IRS-1 bus]
-
A.
IRS-1 bus
chosen
The IRS-1 bus is a standardized Indian satellite platform developed for the Indian Remote Sensing (IRS) series, providing the structural, power, and control systems for Earth observation spacecraft.
-
B.
ISA bus
ISA bus is an early IBM PC expansion bus standard that provided a common hardware interface for adding peripheral cards like sound, network, and graphics adapters.
-
C.
Multibus
Multibus is an early Intel-developed computer bus standard widely used in 1980s workstations and embedded systems for modular expansion and peripheral connectivity.
-
D.
UNIBUS
UNIBUS is a pioneering computer bus architecture developed for Digital Equipment Corporation’s PDP series that unified memory and peripheral communications on a single shared system bus.
-
E.
Element Interconnect Bus
The Element Interconnect Bus is a high-speed internal communication network in the Cell Broadband Engine architecture that links its processing elements and memory controllers to enable efficient parallel data transfer.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d6aa9ccddc8190868998c8b7beb060 |
completed | April 8, 2026, 7:21 p.m. |
| NER | Named-entity recognition | batch_69d7e86e9ef48190b4df4b14319a954f |
completed | April 9, 2026, 5:57 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69e4421d35f48190a5905fbab39f4015 |
completed | April 19, 2026, 2:46 a.m. |
Created at: April 8, 2026, 9:28 p.m.