Triple
T10215738
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | MC88110 |
E242436
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | Motorola 88000 family processor |
C26213
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: Motorola 88000 family processor Context triple: [MC88110, instanceOf, Motorola 88000 family processor]
-
A.
Motorola 88000 family microprocessor
chosen
The Motorola 88000 family microprocessor is a series of 32-bit RISC CPUs developed by Motorola in the late 1980s, designed for high-performance computing and embedded systems with a clean, load-store architecture.
-
B.
Motorola 680x0 family processor
A Motorola 680x0 family processor is a 32-bit CISC microprocessor architecture used in many 1980s–1990s computers and workstations, known for its orthogonal instruction set and influential role in systems like the Apple Macintosh, Amiga, and Atari ST.
-
C.
RISC workstation family
A RISC workstation family is a series of high-performance desktop or server computers built around Reduced Instruction Set Computing processors, designed for technical, scientific, or engineering applications requiring efficient computation and advanced graphics.
-
D.
PowerPC-based processor core
A PowerPC-based processor core is a microprocessor design implementing the PowerPC instruction set architecture, providing the fundamental execution, control, and data-processing capabilities for embedded or general-purpose computing systems.
-
E.
RISC server family
A RISC server family is a line of server systems built around Reduced Instruction Set Computing processors, optimized for high-performance, scalable, and efficient execution of server workloads.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d381ae26c48190985abd0e25ee5d04 |
completed | April 6, 2026, 9:49 a.m. |
Created at: April 6, 2026, 11:05 a.m.