Triple
T10196838
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Multiband Imaging Photometer for Spitzer |
E238783
|
entity |
| Predicate | abbreviation |
P43
|
FINISHED |
| Object |
MIPS
MIPS is an infrared imaging and photometry instrument that operated aboard the Spitzer Space Telescope, used to study celestial objects at multiple mid- to far-infrared wavelengths.
|
E846873
|
NE FINISHED |
How this triple was built (4 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS | Statement: [Multiband Imaging Photometer for Spitzer, abbreviation, MIPS]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS Context triple: [Multiband Imaging Photometer for Spitzer, abbreviation, MIPS]
-
A.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
B.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
-
C.
MIPS III
MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
-
D.
MIPS R2000
The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.
-
E.
MIPS IV
MIPS IV is a 64-bit RISC instruction set architecture in the MIPS family, designed to enhance performance and support advanced computing features over its predecessors.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: MIPS Triple: [Multiband Imaging Photometer for Spitzer, abbreviation, MIPS]
Generated description
MIPS is an infrared imaging and photometry instrument that operated aboard the Spitzer Space Telescope, used to study celestial objects at multiple mid- to far-infrared wavelengths.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: MIPS Target entity description: MIPS is an infrared imaging and photometry instrument that operated aboard the Spitzer Space Telescope, used to study celestial objects at multiple mid- to far-infrared wavelengths.
-
A.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
B.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
-
C.
MIPS III
MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
-
D.
MIPS R2000
The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.
-
E.
MIPS IV
MIPS IV is a 64-bit RISC instruction set architecture in the MIPS family, designed to enhance performance and support advanced computing features over its predecessors.
- F. None of above. chosen
Provenance (5 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ca84e1ea088190b38162e43d4cfa8f |
completed | March 30, 2026, 2:12 p.m. |
| NER | Named-entity recognition | batch_69cdedcaf6688190938d8e56e29493eb |
completed | April 2, 2026, 4:17 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69d317e4a3308190b6ec4252bc55985d |
completed | April 6, 2026, 2:18 a.m. |
| NEDg | Description generation | batch_69d31a2a050081908e5b3a14cf02d227 |
completed | April 6, 2026, 2:27 a.m. |
| NED2 | Entity disambiguation (via description) | batch_69d31acf46008190b6bf1b111e13bfe9 |
completed | April 6, 2026, 2:30 a.m. |
Created at: March 30, 2026, 9:13 p.m.