cacheDesign

P158913 predicate

Indicates that one entity designs, specifies, or defines the structure and behavior of a cache used by another entity or system.

Sample triples (4)

Subject Object
AMD Athlon II (low-end models) emphasis on larger L2 cache instead of L3 cache
Duron reduced L2 cache compared to Athlon
Zen shared L3 cache per CCX
Zen 3 unified 32 MB L3 cache per 8-core CCX