MIPI DSI-2

E917070

MIPI DSI-2 is a high-speed, low-power interface standard defined by the MIPI Alliance for connecting displays to mobile and embedded devices, supporting advanced features such as Display Stream Compression for efficient high-resolution video transmission.

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Statements (49)

Predicate Object
instanceOf MIPI specification
display interface standard
basedOn MIPI C-PHY NERFINISHED
MIPI D-PHY NERFINISHED
compatibleWith MIPI C-PHY physical layer NERFINISHED
MIPI D-PHY physical layer NERFINISHED
definedBy MIPI Alliance NERFINISHED
designedFor AR/VR headsets
IoT devices with displays
automotive displays
smartphones
tablets
enables lower electromagnetic interference
lower power consumption than legacy parallel display interfaces
reduced pin count compared to parallel interfaces
follows MIPI Alliance specification framework NERFINISHED
improvesUpon MIPI DSI bandwidth efficiency
MIPI DSI feature set NERFINISHED
MIPI DSI power efficiency
includes control packets
error-reporting packets
video data packets
predecessor MIPI DSI NERFINISHED
relatedTo MIPI C-PHY NERFINISHED
MIPI CSI-2 NERFINISHED
MIPI D-PHY NERFINISHED
VESA Display Stream Compression NERFINISHED
standardType high-speed serial interface standard
supports Display Stream Compression NERFINISHED
VESA DSC NERFINISHED
command mode
error correction mechanisms
error detection
forward error correction (optional, via DSC ecosystem)
high-resolution video transmission
high-speed data transmission
lane scalability
low-power operation
multiple virtual channels
video mode
targetIndustry automotive
consumer electronics
industrial embedded systems
mobile
usedFor connecting displays to application processors
connecting displays to embedded devices
connecting displays to mobile devices
uses high-speed serial differential signaling
packet-based data transmission

Referenced by (1)

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