Test Access Port
E912830
A Test Access Port (TAP) is the standardized hardware interface defined by the JTAG boundary-scan architecture that provides external access for testing, debugging, and programming integrated circuits and boards.
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
JTAG interface
ⓘ
hardware interface ⓘ test access mechanism ⓘ |
| abbreviation | TAP ⓘ |
| allows |
chained connection of multiple devices
ⓘ
external access to internal test logic ⓘ non-intrusive board-level testing ⓘ |
| connectsTo |
JTAG test equipment
ⓘ
boundary-scan chain ⓘ |
| controls | TAP controller ⓘ |
| definedBy | IEEE 1149.1 NERFINISHED ⓘ |
| enablesAccessTo |
boundary-scan register
ⓘ
data registers ⓘ instruction register ⓘ |
| hasComponent |
TCK pin
ⓘ
TDI pin ⓘ TDO pin ⓘ TMS pin ⓘ |
| hasFullName | Test Access Port NERFINISHED ⓘ |
| hasOptionalComponent | TRST pin ⓘ |
| hasSignalType | synchronous serial ⓘ |
| interpretsControlSignal | TMS NERFINISHED ⓘ |
| isAccessedBy |
JTAG controller
ⓘ
boundary-scan tester ⓘ on-chip debug tools ⓘ |
| isRelatedTo |
boundary-scan testing
ⓘ
design-for-testability ⓘ |
| isStandardizedIn | IEEE 1149.1 boundary-scan standard ⓘ |
| isUsedIn |
ASICs
NERFINISHED
ⓘ
FPGAs NERFINISHED ⓘ digital integrated circuits ⓘ microcontrollers ⓘ system-on-chip devices ⓘ |
| mayIncludeResetSignal | TRST ⓘ |
| operatesWithClock | TCK GENERATED ⓘ |
| outputsDataOn | TDO ⓘ |
| partOf | JTAG boundary-scan architecture ⓘ |
| receivesDataOn | TDI ⓘ |
| supportsOperation |
boundary-scan test
ⓘ
device identification via IDCODE ⓘ in-circuit debugging ⓘ in-system programming ⓘ |
| usedFor |
debugging integrated circuits
ⓘ
debugging printed circuit boards ⓘ programming devices on a board ⓘ programming integrated circuits ⓘ testing integrated circuits ⓘ testing printed circuit boards ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.