Test Access Port
E912830
A Test Access Port (TAP) is the standardized hardware interface defined by the JTAG boundary-scan architecture that provides external access for testing, debugging, and programming integrated circuits and boards.
All labels observed (1)
| Label | Occurrences |
|---|---|
| Test Access Port canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T11226638 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Test Access Port Context triple: [Joint Test Action Group, hasConcept, Test Access Port]
-
A.
SL Access
SL Access is Stockholm's public transport smart card and ticketing system used for travel on buses, trains, and other SL services.
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B.
Port Hacking
Port Hacking is a tidal estuary and bay in southern Sydney, New South Wales, known for its scenic waterways, recreational boating, and proximity to the Royal National Park.
-
C.
DashPass
DashPass is DoorDash’s subscription program that offers members benefits like reduced delivery fees and other savings on food and grocery orders.
-
D.
Aceso
Aceso is a minor Greek goddess associated with the process of healing and the curing of illness.
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E.
ClearAccessIP
ClearAccessIP is a technology company that provides AI-driven intellectual property management and patent analytics solutions for businesses and legal professionals.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: Test Access Port Target entity description: A Test Access Port (TAP) is the standardized hardware interface defined by the JTAG boundary-scan architecture that provides external access for testing, debugging, and programming integrated circuits and boards.
-
A.
SL Access
SL Access is Stockholm's public transport smart card and ticketing system used for travel on buses, trains, and other SL services.
-
B.
Port Hacking
Port Hacking is a tidal estuary and bay in southern Sydney, New South Wales, known for its scenic waterways, recreational boating, and proximity to the Royal National Park.
-
C.
DashPass
DashPass is DoorDash’s subscription program that offers members benefits like reduced delivery fees and other savings on food and grocery orders.
-
D.
Aceso
Aceso is a minor Greek goddess associated with the process of healing and the curing of illness.
-
E.
ClearAccessIP
ClearAccessIP is a technology company that provides AI-driven intellectual property management and patent analytics solutions for businesses and legal professionals.
- F. None of above. chosen
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
JTAG interface
ⓘ
hardware interface ⓘ test access mechanism ⓘ |
| abbreviation | TAP ⓘ |
| allows |
chained connection of multiple devices
ⓘ
external access to internal test logic ⓘ non-intrusive board-level testing ⓘ |
| connectsTo |
JTAG test equipment
ⓘ
boundary-scan chain ⓘ |
| controls | TAP controller ⓘ |
| definedBy | IEEE 1149.1 NERFINISHED ⓘ |
| enablesAccessTo |
boundary-scan register
ⓘ
data registers ⓘ instruction register ⓘ |
| hasComponent |
TCK pin
ⓘ
TDI pin ⓘ TDO pin ⓘ TMS pin ⓘ |
| hasFullName | Test Access Port NERFINISHED ⓘ |
| hasOptionalComponent | TRST pin ⓘ |
| hasSignalType | synchronous serial ⓘ |
| interpretsControlSignal | TMS NERFINISHED ⓘ |
| isAccessedBy |
JTAG controller
ⓘ
boundary-scan tester ⓘ on-chip debug tools ⓘ |
| isRelatedTo |
boundary-scan testing
ⓘ
design-for-testability ⓘ |
| isStandardizedIn | IEEE 1149.1 boundary-scan standard ⓘ |
| isUsedIn |
ASICs
NERFINISHED
ⓘ
FPGAs NERFINISHED ⓘ digital integrated circuits ⓘ microcontrollers ⓘ system-on-chip devices ⓘ |
| mayIncludeResetSignal | TRST ⓘ |
| operatesWithClock | TCK GENERATED ⓘ |
| outputsDataOn | TDO ⓘ |
| partOf | JTAG boundary-scan architecture ⓘ |
| receivesDataOn | TDI ⓘ |
| supportsOperation |
boundary-scan test
ⓘ
device identification via IDCODE ⓘ in-circuit debugging ⓘ in-system programming ⓘ |
| usedFor |
debugging integrated circuits
ⓘ
debugging printed circuit boards ⓘ programming devices on a board ⓘ programming integrated circuits ⓘ testing integrated circuits ⓘ testing printed circuit boards ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: Test Access Port Description of subject: A Test Access Port (TAP) is the standardized hardware interface defined by the JTAG boundary-scan architecture that provides external access for testing, debugging, and programming integrated circuits and boards.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.