Yices

E904160
SMT solver decision procedure formal verification tool software tool

Yices is a high-performance Satisfiability Modulo Theories (SMT) solver widely used in formal verification and automated reasoning.

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Statements (44)

Predicate Object
instanceOf SMT solver ⓘ
decision procedure ⓘ
formal verification tool ⓘ
software tool ⓘ
conformsTo SMT-LIB standard NERFINISHED ⓘ
hasDeveloper SRI International NERFINISHED ⓘ
SRI International Computer Science Laboratory NERFINISHED ⓘ
hasHomepage https://yices.csl.sri.com/ ⓘ
hasLicense proprietary with free academic use ⓘ
hasProperty high-performance ⓘ
industrial-strength ⓘ
supports multiple background theories ⓘ
hasVersion Yices 1 NERFINISHED ⓘ
Yices 2 NERFINISHED ⓘ
isDesignedFor automated reasoning ⓘ
formal verification ⓘ
hardware verification ⓘ
model checking ⓘ
software verification ⓘ
isNamedAfter Yices (proper name used by SRI International) NERFINISHED ⓘ
isUsedIn formal methods research ⓘ
industrial verification workflows ⓘ
isWrittenInLanguage C NERFINISHED ⓘ
participatesIn SMT-COMP NERFINISHED ⓘ
runsOn Linux ⓘ
Windows NERFINISHED ⓘ
macOS NERFINISHED ⓘ
supportsFeature incremental solving ⓘ
model generation ⓘ
optimization for some theories ⓘ
push-pop interface ⓘ
unsat core extraction ⓘ
supportsInterface C API NERFINISHED ⓘ
C++ API NERFINISHED ⓘ
Python bindings ⓘ
SMT-LIB format ⓘ
command-line interface ⓘ
supportsLogic Satisfiability Modulo Theories NERFINISHED ⓘ
arrays ⓘ
bit-vectors ⓘ
combinations of theories ⓘ
equality with uninterpreted functions ⓘ
quantifier-free linear arithmetic ⓘ
uninterpreted functions ⓘ

Referenced by (1)

Full triples — surface form annotated when it differs from this entity's canonical label.

Satisfiability Modulo Theories (SMT) → hasSolver → Yices ⓘ
subject surface form: Satisfiability Modulo Theories