ARC 600 family
E845864
The ARC 600 family is a series of configurable 32-bit embedded processor cores from Synopsys’ ARC architecture line, designed for low-power, high-efficiency applications in SoCs.
All labels observed (1)
| Label | Occurrences |
|---|---|
| ARC 600 family canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T10167890 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: ARC 600 family Context triple: [ARC, hasVariant, ARC 600 family]
-
A.
Honeywell Level 6 series
The Honeywell Level 6 series is a family of 16-bit minicomputers introduced by Honeywell in the 1970s, widely used for real-time control, industrial automation, and multi-user business applications.
-
B.
Apollo DN500 series
The Apollo DN500 series was a line of 1980s Apollo Computer workstations known for their advanced graphics and networking capabilities in technical and engineering environments.
-
C.
Honeywell 6000 series
The Honeywell 6000 series was a family of mainframe computers from the 1960s and 1970s known for supporting advanced time-sharing operating systems such as Multics.
-
D.
AR 600-20
AR 600-20 is a key U.S. Army regulation that outlines the Army Command Policy, including command responsibilities, Soldier conduct, and the Army’s Equal Opportunity and Sexual Harassment/Assault Response and Prevention (SHARP) programs.
-
E.
Q‑Series
Q‑Series is the marketing name used for later models of the De Havilland Canada Dash 8 turboprop airliners that feature advanced cabin noise and vibration reduction technology.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: ARC 600 family Target entity description: The ARC 600 family is a series of configurable 32-bit embedded processor cores from Synopsys’ ARC architecture line, designed for low-power, high-efficiency applications in SoCs.
-
A.
Honeywell Level 6 series
The Honeywell Level 6 series is a family of 16-bit minicomputers introduced by Honeywell in the 1970s, widely used for real-time control, industrial automation, and multi-user business applications.
-
B.
Apollo DN500 series
The Apollo DN500 series was a line of 1980s Apollo Computer workstations known for their advanced graphics and networking capabilities in technical and engineering environments.
-
C.
Honeywell 6000 series
The Honeywell 6000 series was a family of mainframe computers from the 1960s and 1970s known for supporting advanced time-sharing operating systems such as Multics.
-
D.
AR 600-20
AR 600-20 is a key U.S. Army regulation that outlines the Army Command Policy, including command responsibilities, Soldier conduct, and the Army’s Equal Opportunity and Sexual Harassment/Assault Response and Prevention (SHARP) programs.
-
E.
Q‑Series
Q‑Series is the marketing name used for later models of the De Havilland Canada Dash 8 turboprop airliners that feature advanced cabin noise and vibration reduction technology.
- F. None of above. chosen
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
32-bit processor core family
ⓘ
configurable processor architecture ⓘ embedded processor core family ⓘ |
| acquiredBy | Synopsys NERFINISHED ⓘ |
| architectureFamilyOf |
ARC 610D
NERFINISHED
ⓘ
ARC 620D NERFINISHED ⓘ ARC 625D NERFINISHED ⓘ ARC 650D NERFINISHED ⓘ ARC 670D NERFINISHED ⓘ |
| belongsTo | ARC processor family NERFINISHED ⓘ |
| bitWidth | 32-bit ⓘ |
| configurability | highly configurable ⓘ |
| designedFor |
embedded systems
ⓘ
high-efficiency applications ⓘ low-power applications ⓘ system-on-chip designs ⓘ |
| developer | Synopsys NERFINISHED ⓘ |
| introducedBy | ARC International NERFINISHED ⓘ |
| isaFamily | ARC ISA NERFINISHED ⓘ |
| marketPosition | low-power embedded control core ⓘ |
| optimizationGoal |
area efficiency
ⓘ
performance efficiency ⓘ |
| partOf | Synopsys ARC architecture line NERFINISHED ⓘ |
| powerCharacteristic | low power consumption ⓘ |
| predecessorOf | ARC 700 family NERFINISHED ⓘ |
| primaryAttribute |
configurability for SoC integration
ⓘ
low gate count implementation ⓘ |
| supports |
AMBA-based system interfaces
ⓘ
C and C++ programming ⓘ Harvard architecture variants ⓘ configurable cache options ⓘ configurable instruction set ⓘ debug features ⓘ embedded memory interfaces ⓘ interrupt handling ⓘ optional DSP-style instructions ⓘ optional hardware multipliers ⓘ tightly coupled memory ⓘ user-defined extensions ⓘ |
| targetUseCase |
control processing in SoCs
ⓘ
cost-sensitive embedded devices ⓘ |
| toolchain |
GCC-based toolchains for ARC
ⓘ
Synopsys MetaWare Development Toolkit NERFINISHED ⓘ |
| typicalClockFrequencyRange | hundreds of MHz ⓘ |
| usedIn |
automotive SoCs
ⓘ
consumer electronics SoCs ⓘ industrial control SoCs ⓘ storage controllers ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: ARC 600 family Description of subject: The ARC 600 family is a series of configurable 32-bit embedded processor cores from Synopsys’ ARC architecture line, designed for low-power, high-efficiency applications in SoCs.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.