Mark Liu
E839051
Mark Liu is a prominent Taiwanese semiconductor executive best known as the former chairman of Taiwan Semiconductor Manufacturing Company (TSMC), a leading global chip foundry.
All labels observed (1)
| Label | Occurrences |
|---|---|
| Mark Liu canonical | 1 |
Statements (44)
| Predicate | Object |
|---|---|
| instanceOf |
Taiwanese person
ⓘ
business executive ⓘ semiconductor executive ⓘ |
| almaMater |
National Taiwan University
NERFINISHED
ⓘ
University of California, Berkeley NERFINISHED ⓘ |
| associatedWith |
TSMC’s international expansion
ⓘ
advanced chip fabrication ⓘ foundry business model ⓘ |
| boardMemberOf | TSMC NERFINISHED ⓘ |
| countryOfCitizenship | Taiwan NERFINISHED ⓘ |
| degree |
PhD in electrical engineering
ⓘ
bachelor’s degree in electrical engineering ⓘ |
| educatedAt |
National Taiwan University
NERFINISHED
ⓘ
University of California, Berkeley ⓘ |
| employer |
AT&T Bell Laboratories
NERFINISHED
ⓘ
Taiwan Semiconductor Manufacturing Company NERFINISHED ⓘ |
| field | semiconductor industry ⓘ |
| hasHonor | recognition as a leading figure in the semiconductor industry ⓘ |
| hasRole |
corporate leader
ⓘ
technology strategist ⓘ |
| industry |
integrated circuit manufacturing
ⓘ
semiconductors ⓘ |
| knownFor |
chairmanship of TSMC
ⓘ
leadership at Taiwan Semiconductor Manufacturing Company ⓘ |
| languageSpoken |
English
ⓘ
Mandarin Chinese ⓘ |
| memberOf | board of directors of TSMC ⓘ |
| name | Mark Liu NERFINISHED ⓘ |
| nationality | Taiwanese ⓘ |
| nativeName | 劉德音 NERFINISHED ⓘ |
| notableAchievement | helping TSMC maintain leading position in advanced chip manufacturing ⓘ |
| notableWork |
expansion of TSMC’s advanced process technology capacity
ⓘ
strategic leadership in global foundry market ⓘ |
| partOf | global semiconductor ecosystem ⓘ |
| positionHeld |
chairman of TSMC
ⓘ
chief operating officer of TSMC ⓘ president and co-CEO of TSMC ⓘ researcher at AT&T Bell Laboratories ⓘ senior vice president of operations at TSMC ⓘ |
| residence | Taiwan NERFINISHED ⓘ |
| workFocus |
advanced process nodes
ⓘ
semiconductor manufacturing efficiency ⓘ wafer fabrication capacity planning ⓘ |
| workLocation | Hsinchu, Taiwan NERFINISHED ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.