POWER4 microarchitecture

E826847

The POWER4 microarchitecture is IBM’s high-performance 64-bit RISC processor design that introduced multi-core server CPUs and formed the basis for later PowerPC and POWER family chips.

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Predicate Object
instanceOf IBM POWER architecture
microarchitecture
addressSpace 64-bit virtual address space
architectureFamily POWER NERFINISHED
PowerPC NERFINISHED
architectureType RISC
bitWidth 64-bit
branchPrediction dynamic branch prediction
cacheHierarchy multi-level cache
clockFrequencyRange 1.0–1.9 GHz
coreCountPerDie 2
designer IBM NERFINISHED
endianSupport big-endian
executionModel out-of-order execution
family IBM POWER4 family NERFINISHED
firstImplementedIn IBM POWER4 NERFINISHED
floatingPointUnit integrated high-performance FPU
floatingPointUnitCount multiple FP execution units
influenced POWER5 microarchitecture NERFINISHED
later IBM PowerPC server processors
instructionSetArchitecture PowerPC ISA NERFINISHED
integerUnit multiple integer execution units
introductionYear 2001
L2Cache on-chip L2 cache
L3Cache off-chip L3 cache support
marketPosition high-end
notableContribution early commercial multi-core server CPU design
notableFeature designed for high-performance servers
integrated two processor cores on a single die
introduced dual-core server processors for IBM POWER line
pipelineType superscalar
powerManagement server-oriented power and thermal design
predecessor POWER3 microarchitecture NERFINISHED
primaryUse commercial and technical computing workloads
datacenter workloads
processTechnology 180 nm CMOS
simultaneousMultithreading not supported
succeededBy POWER5 microarchitecture NERFINISHED
supports hardware partitioning in server systems
symmetric multiprocessing
targetMarket enterprise servers
high-end UNIX servers
usedIn IBM RS/6000 servers NERFINISHED
IBM pSeries servers NERFINISHED
vendor IBM NERFINISHED
virtualMemorySupport yes

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PowerPC G5 basedOn POWER4 microarchitecture