Sanjit A. Seshia

E822881

Sanjit A. Seshia is a prominent computer scientist known for his contributions to formal methods and automated verification in engineering and computer science.

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Sanjit A. Seshia canonical 1

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Predicate Object
instanceOf computer scientist
researcher
awardReceived ACM Fellow NERFINISHED
CAV Award NERFINISHED
Guggenheim Fellowship
IEEE Fellow NERFINISHED
NSF CAREER Award NERFINISHED
Presidential Early Career Award for Scientists and Engineers NERFINISHED
basedIn Berkeley, California NERFINISHED
countryOfCitizenship United States of America
educatedAt Carnegie Mellon University NERFINISHED
Indian Institute of Technology Bombay NERFINISHED
employer University of California, Berkeley
ethnicGroup Indian
fieldOfWork artificial intelligence safety
automated verification
computer-aided verification
cyber-physical systems
design automation
formal methods
model checking
satisfiability modulo theories
hasAcademicDegree Bachelor of Technology in Computer Science and Engineering
PhD in Computer Science
hasResearchArea computer science
electrical engineering
hasRole faculty member in Electrical Engineering and Computer Sciences at UC Berkeley
research group leader in formal methods and cyber-physical systems
hasWritten research papers on counterexample-guided abstraction refinement
research papers on formal methods for AI and machine learning
research papers on satisfiability modulo theories
research papers on verification of cyber-physical systems
languageSpoken English
memberOf Association for Computing Machinery NERFINISHED
Institute of Electrical and Electronics Engineers NERFINISHED
notableFor applications of formal methods to AI and machine learning
applications of formal methods to cyber-physical systems
work on counterexample-guided abstraction refinement (CEGAR)
work on satisfiability modulo theories (SMT)
notableWork textbook on formal methods and models for system design
occupation Professor of Electrical Engineering and Computer Sciences
researchInterest design of reliable and secure systems
formal verification of hardware and software
synthesis from formal specifications
verification of autonomous systems
workInstitution University of California, Berkeley NERFINISHED

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