KA10
E817470
KA10 was the original 36-bit processor model used in Digital Equipment Corporation's early DECsystem-10 mainframe computers.
Statements (47)
| Predicate | Object |
|---|---|
| instanceOf |
DECsystem-10 processor
ⓘ
central processing unit ⓘ computer processor ⓘ |
| addressingMode | 36-bit word addressing ⓘ |
| alsoKnownAs | PDP-10 KA10 processor NERFINISHED ⓘ |
| architecture | 36-bit architecture ⓘ |
| bitWidth | 36 ⓘ |
| category | mainframe CPU ⓘ |
| companyDivision | DEC Large Computer Products NERFINISHED ⓘ |
| countryOfOrigin |
United States of America
ⓘ
surface form:
United States
|
| dataPathWidth | 36 bits ⓘ |
| designedFor |
mainframe computers
ⓘ
time-sharing systems ⓘ |
| family | PDP-10 NERFINISHED ⓘ |
| floatingPointFormat | 36-bit floating point ⓘ |
| implementation | wire-wrapped backplanes ⓘ |
| instructionSetArchitecture | PDP-10 instruction set ⓘ |
| instructionType | CISC ⓘ |
| introductionDate | 1967 ⓘ |
| manufacturer | Digital Equipment Corporation NERFINISHED ⓘ |
| marketedAs | DECsystem-10 processor ⓘ |
| notableInstallation |
Carnegie Mellon University
NERFINISHED
ⓘ
MIT NERFINISHED ⓘ Stanford University NERFINISHED ⓘ |
| operatingSystem |
TENEX (on modified systems)
NERFINISHED
ⓘ
TOPS-10 NERFINISHED ⓘ |
| partOf |
DECsystem-10 mainframe
NERFINISHED
ⓘ
PDP-10 line NERFINISHED ⓘ |
| primaryUse |
academic computing
ⓘ
research computing ⓘ time-sharing service bureaus ⓘ |
| registerWidth | 36 bits ⓘ |
| role | original processor for DECsystem-10 ⓘ |
| successor |
KI10
ⓘ
KL10 ⓘ KS10 ⓘ |
| supports |
batch processing
ⓘ
floating-point operations ⓘ hardware divide ⓘ hardware multiply ⓘ time-sharing ⓘ |
| technology | discrete transistor logic ⓘ |
| usedFor |
early ARPANET hosts
ⓘ
time-sharing operating system development ⓘ |
| usedIn |
DECsystem-10
NERFINISHED
ⓘ
PDP-10 family NERFINISHED ⓘ |
| wordSize | 36-bit ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.