Spike

E736982

RISC-V instruction set simulator reference simulator software tool

Spike is a reference RISC-V instruction set simulator used to model, test, and validate RISC-V processor implementations.

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Statements (31)

Predicate	Object
instanceOf	RISC-V instruction set simulator ⓘ reference simulator ⓘ software tool ⓘ
developedBy	RISC-V community NERFINISHED ⓘ
executionMode	instruction set simulation ⓘ
hasFeature	command-line interface ⓘ configurable ISA features ⓘ cycle-approximate functional simulation ⓘ support for multiple RISC-V cores in one simulation ⓘ
implementationLanguage	C++ NERFINISHED ⓘ
license	open source license ⓘ
partOfEcosystem	RISC-V software and tooling ecosystem ⓘ
repositoryHosting	GitHub NERFINISHED ⓘ
simulates	RISC-V cores ⓘ RISC-V instructions ⓘ
supports	RISC-V privileged architecture ⓘ RISC-V user-level ISA ⓘ multiple RISC-V extensions ⓘ
supportsArchitecture	RISC-V NERFINISHED ⓘ
targetUsers	RISC-V implementers ⓘ RISC-V researchers ⓘ
usedAs	golden reference model for RISC-V ISA ⓘ
usedBy	RISC-V software developers ⓘ hardware designers ⓘ verification engineers ⓘ
usedFor	ISA compliance checking ⓘ debugging RISC-V software ⓘ early software bring-up ⓘ modeling RISC-V processor implementations ⓘ testing RISC-V processor implementations ⓘ validating RISC-V processor implementations ⓘ

Full triples — surface form annotated when it differs from this entity's canonical label.

Spike RISC-V ISA simulator → name → Spike ⓘ

Spike RISC-V ISA simulator → shortName → Spike ⓘ