J-Core architecture
E724212
J-Core architecture is an open-source, FPGA-oriented implementation of the SuperH-compatible CPU design used in embedded systems and hobbyist hardware projects.
Statements (29)
| Predicate | Object |
|---|---|
| instanceOf |
FPGA-oriented processor design
ⓘ
SuperH-compatible CPU core ⓘ open-source CPU architecture ⓘ |
| applicationDomain |
education and experimentation
ⓘ
embedded computing ⓘ |
| compatibleWith |
SuperH ISA
NERFINISHED
ⓘ
SuperH-2 instruction set NERFINISHED ⓘ |
| designedFor | FPGA implementation ⓘ |
| goal |
enable open hardware designs
ⓘ
provide a libre SuperH-compatible CPU core ⓘ |
| hasFeature |
RISC architecture
ⓘ
fixed-length instructions ⓘ memory-mapped I/O ⓘ support for interrupts ⓘ support for timers ⓘ |
| hasProperty |
little-endian
ⓘ
soft-core CPU ⓘ synthesizable in HDL ⓘ |
| implements | SuperH-compatible CPU design ⓘ |
| isOpenSource | true ⓘ |
| isSoftCore | true ⓘ |
| license | open-source license ⓘ |
| supports |
C programming language toolchains
ⓘ
GCC-based toolchains ⓘ |
| targetPlatform | FPGA development boards ⓘ |
| typicalUseCase |
custom SoC designs on FPGA
ⓘ
open hardware experimentation ⓘ |
| usedIn |
embedded systems
ⓘ
hobbyist hardware projects ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.